1. Field
Embodiments of the present invention relate to computers and, in particular, to microprocessor clock generators.
2. Discussion of Related Art
Microprocessors use many different clocks to synchronize the operations of the various circuits inside the microprocessor. For example, one clock may determine the speed at which the microprocessor core runs (microprocessor core clock). Some microprocessors are designed such that the microprocessor core clock has a duty cycle of approximately fifty percent. A clock generator is normally used to generate the microprocessor core clock.
A limitation of clock signals is that their duty cycles are frequency dependent. The situation worsens when a clock signal propagates across power domains. For example, when the clock signal has to cross power domains, the clock signal pulse shape will change. The rising edges and falling edges of the clock signal will become asymmetrical (e.g., the duty cycle is no longer fifty percent).
One common way of ameliorating this situation is to have the power supply to the clock generator be the same as the power supply to the microprocessor core. For example, the power supply to the microprocessor and the clock generator can be maintained at 1.3 volts.
This solution may be feasible to maintain duty cycle performance on a very small scale, but has its drawbacks. For example, this solution is not very versatile. In general, the more products the clock generator/microprocessor combination is compatible with the better. Sometimes a server application may run better when the clock generator operates at 1.3 volts VCC (or VDD) and the microprocessor operates at 1.7 volts VCC. A desktop application may run better when the clock generator operates at 1.5 volts VCC and the microprocessor operates at 1.7 volts VCC. A mobile application may run better when the clock generator operates at 1.3 volts VCC and the microprocessor operates at 1.0 volt VCC. Thus, although adequate, this approach has its limitations.
Another traditional way of making this situation better is to allow the clock to cross power domains but then in the destination domain to apply a divide-by-two function to the rising edges of the clock generator output to obtain the microprocessor core clock signal. Because the divide-by-two approach uses only the rising edges of clock generator output to determine both rising and falling edges of the microprocessor core clock signal the clock generator output duty cycle is irrelevant to the microprocessor core clock signal duty cycle. As long as the clock generator output period is stable, the microprocessor core clock signal duty cycle will be fifty percent. Because of this same reason, the clock generator output can be distributed across power domains while maintaining microprocessor core clock signal symmetry.
A drawback to this approach is that as technology advances its implementation becomes quite expensive. In general, the less expensive individual components are for a computer, the less expensive the computer. For a clock generator to work with state of the art microprocessors that operate at three gigahertz (GHz), for example, the clock generator must output a six GHz clock signal. As the frequency of the clock generator increases, its complexity increases. As the complexity of the clock generator circuit increases, it becomes a less attractive technique to construct a microprocessor core clock signal that has a duty cycle of approximately fifty percent across power domains. This is because the area that the clock generator consumes increases. The clock generator also consumes more power.